Flip-Flop Explorer

CSC-116 · Semester I · Digital Logic

intermediate30 minAvailable

Live simulation0 components · 0 wires

Your canvas is empty

Add inputs (Switch / Clock), gates, and an output lamp from the palette, or load a starter preset from the toolbar above.

Click a switch to toggle it · drag output → input to wire · drag to move · Delete removes the selection · Ctrl+Z undoes.

The truth table appears when the circuit has at least one switch and one output lamp.

Lab brief

Objective

Build SR, D, JK and T flip-flops from logic gates on a blank canvas and verify their characteristic behaviour: set, reset, hold and toggle.

Theory & concepts

Flip-flops are the memory cells of digital systems. The simplest is the SR latch built from two cross-coupled NAND or NOR gates: it stores one bit and can be set or reset. Edge-triggered D, JK and T flip-flops refine this idea so changes happen only on a clock edge.

Rendering diagram…

From SR latch to D and JK flip-flops

SR latch (NAND form):  Q = (S NAND NOT Q);  NOT Q = (R NAND Q)
D flip-flop:           Q captures D at the clock edge, holds otherwise
JK flip-flop:          J=1,K=1 toggles Q; J=1,K=0 sets; J=0,K=1 resets
T flip-flop:           toggles Q on every active clock edge

On the blank canvas you start with no gates. Build the cross-coupled pair, add switches for the inputs and LEDs for Q and its complement, then step through the truth table to confirm each behaviour.

Prerequisites

Lesson: Flip-flops: SR, D, JK and T
Lesson: Sequential logic: memory and clocking

Instructions

1Start from the blank preset with a clean canvas.
2Add two NAND (or NOR) gates and cross-couple them to form an SR latch.
3Add switches for S and R and LEDs for Q and Q'.
4Step through the SR truth table and record the outputs.
5Extend the circuit toward an edge-triggered D flip-flop by adding a clock input.
6Compare with a JK configuration and observe the toggle behaviour.

Tasks

Build an SR latch
Cross-couple two gates and verify set/reset/hold.
Verify the truth table
Step S=1, R=0 then S=0, R=0 and confirm Q holds.
Add a clocked D stage
Show that D is captured only at the clock edge.
Explore toggle
Configure JK so J=K=1 and observe Q toggling.

Self-check

The SR latch truth table matches the expected behaviour.
The student explains why the invalid S=R=1 state is avoided.
The clocked version captures D only at the edge.
The toggle behaviour of JK (J=K=1) is demonstrated.

Environment

gate paletteclock sourcewire connectionslive simulation