Pipeline Timing Visualizer
5-stage pipeline — I2 depends on I1's result (RAW hazard).
| IF | ID | EX | MEM | WB | |
|---|---|---|---|---|---|
| I1: ADD R1, R2, R3 | ID | ||||
| I2: SUB R4, R1, R5 | IF | ||||
| I3: MUL R6, R7, R8 | |||||
| I4: LD R9, [R10] |
Without a stall, I2 reads R1 in EX at cycle 3 before I1 writes it in WB at cycle 5 — a read-after-write hazard. Compilers insert nops or the hardware forwards/stalls. One stalled cycle shifts every later stage by one.